5M1270ZF256C5N Datasheet, PDF (29/30 Pages) Altera Corporation – DC and Switching Characteristics for MAX V Devices

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
3–29
JTAG Timing Specifications
Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device
family.
Figure 3–6. JTAG Timing Waveform for MAX V Devices
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t_JPH
t_JPXZ
t_JSXZ
Table 3–41 lists the JTAG timing parameters and values for the MAX V device family.
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
Symbol
t_JCP (1)
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
Parameter
TCK clock period for V_CCIO1 = 3.3 V
TCK clock period for V_CCIO1 = 2.5 V
TCK clock period for V_CCIO1 = 1.8 V
TCK clock period for V_CCIO1 = 1.5 V
TCK clock high time
TCK clock low time
JTAG port setup time (2)
JTAG port hold time
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Min
Max
Unit
55.5
—
ns
62.5
—
ns
100
—
ns
143
—
ns
20
—
ns
20
—
ns
8
—
ns
10
—
ns
—
15
ns
—
15
ns
—
15
ns
8
—
ns
10
—
ns
—
25
ns
—
25
ns
May 2011 Altera Corporation
MAX V Device Handbook