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5M1270ZF256C5N Datasheet, PDF (22/30 Pages) Altera Corporation – DC and Switching Characteristics for MAX V Devices | |||
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3â22
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3â30 lists the external I/O timing parameters for the F324 package of the
5M1270Z device.
Table 3â30. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)
Symbol
Parameter
Condition
C4
Min
Max
C5, I5
Unit
Min
Max
tPD1
Worst case pin-to-pin delay through one LUT 10 pF
â
9.1
â
11.2 ns
tPD2
Best case pin-to-pin delay through one LUT
10 pF
â
4.8
â
5.9
ns
tSU
Global clock setup time
â
1.5
â
1.9
â
ns
tH
Global clock hold time
â
0
â
0
â
ns
tCO
Global clock to output delay
10 pF
2.0
6.0
2.0
7.4
ns
tCH
Global clock high time
â
216
â
266
â
ps
tCL
Global clock low time
â
216
â
266
â
ps
tCNT
Minimum global clock period for 16-bit
counter
â
4.0
â
5.0
â
ns
fCNT
Maximum global clock frequency for 16-bit
counter
â
â
247.5
â
201.1 MHz
Notes to Table 3â30:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Only applicable to the F324 package of the 5M1270Z device.
Table 3â31 lists the external I/O timing parameters for the 5M2210Z device.
Table 3â31. Global Clock External I/O Timing Parameters for the 5M2210Z Device (Note 1)
Symbol
Parameter
Condition
C4
Min
Max
C5, I5
Unit
Min
Max
tPD1
Worst case pin-to-pin delay through one LUT 10 pF
â
9.1
â
11.2 ns
tPD2
Best case pin-to-pin delay through one LUT
10 pF
â
4.8
â
5.9
ns
tSU
Global clock setup time
â
1.5
â
1.9
â
ns
tH
Global clock hold time
â
0
â
0
â
ns
tCO
Global clock to output delay
10 pF
2.0
6.0
2.0
7.4
ns
tCH
Global clock high time
â
216
â
266
â
ps
tCL
Global clock low time
â
216
â
266
â
ps
tCNT
Minimum global clock period for 16-bit
counter
â
4.0
â
5.0
â
ns
fCNT
Maximum global clock frequency for 16-bit
counter
â
â
247.5
â
201.1 MHz
Note to Table 3â31:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
MAX V Device Handbook
May 2011 Altera Corporation
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