5CEBA9F23C7N Datasheet, PDF (27/58 Pages) Altera Corporation – Cyclone V Device Datasheet

Switching Characteristics
Page 27
Memory Block Specifications
Table 26 lists the Cyclone V memory block specifications.
To achieve the maximum memory block performance, use a memory block clock that
comes through global clock routing from an on-chip PLL and set to 50% output duty
cycle. Use the Quartus II software to report timing for the memory block clocking
schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no
degradation in f_MAX.
Table 26. Memory Block Performance Specifications for Cyclone V Devices—Preliminary
Memory
Mode
MLAB
M10K
Block
Single port, all supported widths
Simple dual-port, all supported
widths
Simple dual-port with read and
write at the same address
ROM, all supported width
Single-port, all supported widths
Simple dual-port, all supported
widths
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
True dual port, all supported
widths
ROM, all supported widths
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
Resources Used
ALUTs Memory
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
Performance
Unit
–C6
–C7, –I7 –C8, –A7
420
350
300
MHz
420
350
300
MHz
340
290
240
MHz
420
350
300
MHz
315
275
240
MHz
315
275
240
MHz
275
240
180
MHz
315
315
1,450
1,000
275
275
1,550
1,200
240
MHz
240
MHz
1,650
ps
1,350
ps
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
1 Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
June 2013 Altera Corporation
Cyclone V Device Datasheet