EPF10K10LC84-4 Datasheet, PDF (23/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 10. LE Clear & Preset Modes
Asynchronous Clear
VCC
PRN
DQ
labctrl1 or
labctrl2
Chip-Wide Reset
CLRN
Asynchronous Preset
Chip-Wide Reset
labctrl1 or
labctrl2
PRN
DQ
CLRN
VCC
Asynchronous Clear & Preset
labctrl1
PRN
DQ
labctrl2
Chip-Wide Reset
CLRN
Asynchronous Load with Clear
labctrl1
(Asynchronous
Load)
NOT
data3
(Data)
labctrl2
(Clear)
Chip-Wide Reset
NOT
Asynchronous Load with Preset
labctrl1
(Asynchronous
Load)
labctrl2
(Preset)
NOT
data3
(Data)
NOT
PRN
DQ
CLRN
Asynchronous Load without Clear or Preset
labctrl1
(Asynchronous
Load)
data3
(Data)
NOT
PRN
DQ
NOT
CLRN
Chip-Wide Reset
PRN
DQ
CLRN
Chip-Wide Reset
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to V_CC to deactivate it.
Altera Corporation
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