EP3C16E144C7N Datasheet, PDF (16/34 Pages) Altera Corporation – This chapter describes the electric characteristics, switching characteristics, and I/O timing for Cyclone® III devices. A glossary is also included for your reference.

1–16
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–20. Cyclone III Devices PLL Specifications ⁽¹⁾ (Part 2 of 2)
Symbol
Parameter
Min Typ Max
Unit
f_SCANCLK
scanclk frequency
—
—
100
MHz
Notes to Table 1–20:
(1) V_{CCD_PLL} should always be connected to V_CCINT through decoupling capacitor and ferrite bead.
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The V_CO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V_CO post-scale
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCO specification.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
jitter of the PLL, when an input jitter of 30 ps is applied.
(6) With 100 MHz scanclk frequency.
Embedded Multiplier Specifications
Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications
Mode
Resources Used
Performance
Unit
Number of Multipliers
C6
C7, I7, A7
C8
9 × 9-bit
multiplier
18 × 18-bit
multiplier
1
340
300
260
MHz
1
287
250
200
MHz
Memory Block Specifications
Table 1–22 describes the M9K memory block specifications for Cyclone III devices.
Table 1–22. Cyclone III Devices Memory Block Performance Specifications
Memory
Mode
Resources Used
Performance
LEs
M9K
Memory
C6
C7, I7, A7
C8
Unit
M9K Block
FIFO 256 × 36
47
Single-port 256 × 36
0
Simple dual-port 256 × 36 CLK
0
True dual port 512 × 18 single CLK 0
1
315
274
238
MHz
1
315
274
238
MHz
1
315
274
238
MHz
1
315
274
238
MHz
Configuration and JTAG Specifications
Table 1–23 lists the configuration mode specifications for Cyclone III devices.
Table 1–23. Cyclone III Devices Configuration Mode Specifications
Programming Mode
DCLK F_max
Unit
Passive Serial (PS)
133
MHz
Fast Passive Parallel (FPP) ⁽¹⁾
100
MHz
Note to Table 1–23:
(1) EP3C40 and smaller density members support 133 MHz.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation