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EP3C16E144C7N Datasheet, PDF (15/34 Pages) Altera Corporation – This chapter describes the electric characteristics, switching characteristics, and I/O timing for Cyclone® III devices. A glossary is also included for your reference. | |||
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Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
1â15
PLL Specifications
Table 1â20 describes the PLL specifications for Cyclone III devices when operating in
the commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (â40°C to 100°C), and the automotive junction temperature range
(â40°Cto 125°C). For more information about PLL block, refer to âPLL Blockâ in
âGlossaryâ on page 1â27.
Table 1â20. Cyclone III Devices PLL Specifications (1) (Part 1 of 2)
fIN (2)
fINPFD
fVCO (3)
fINDUTY
Symbol
tINJITTER_CCJ (4)
fOUT_EXT (external clock output)
(2)
Parameter
Input clock frequency
PFD input frequency
PLL internal VCO operating range
Input clock duty cycle
Input clock cycle-to-cycle jitter for FINPFD ï³ 100 MHz
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz
PLL output frequency
Min Typ Max
Unit
5
â 472.5
MHz
5
â
325
MHz
600
â 1300
MHz
40
â
60
%
â
â
0.15
UI
â
â ±750
ps
â
â 472.5
MHz
fOUT (to global clock)
tOUTDUTY
tLOCK
tDLOCK
tOUTJITTER_PERIOD_DEDCLK (5)
tOUTJITTER_CCJ_DEDCLK (5)
tOUTJITTER_PERIOD_IO (5)
tOUTJITTER_CCJ_IO (5)
tPLL_PSERR
tARESET
tCONFIGPLL
PLL output frequency (â6 speed grade)
â
â 472.5
MHz
PLL output frequency (â7 speed grade)
â
â
450
MHz
PLL output frequency (â8 speed grade)
â
â 402.5
MHz
Duty cycle for external clock output (when set to 50%) 45
50
55
%
Time required to lock from end of device configuration â
â
1
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
â
â
1
ms
areset is deasserted)
Dedicated clock output period jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Regular I/O period jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Regular I/O cycle-to-cycle jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Accuracy of PLL phase shift
â
â
300
ps
â
â
30
mUI
â
â
300
ps
â
â
30
mUI
â
â
650
ps
â
â
75
mUI
â
â
650
ps
â
â
75
mUI
â
â
±50
ps
Minimum pulse width on areset signal.
10
â
â
ns
Time required to reconfigure scan chains for PLLs
â
3.5 (6)
â
SCANCLK
cycles
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
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