EP3C16E144C8N Datasheet, PDF (15/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet

Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
1–15
PLL Specifications
Table 1–20 describes the PLL specifications for Cyclone III devices when operating in
the commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), and the automotive junction temperature range
(–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in
“Glossary” on page 1–27.
Table 1–20. Cyclone III Devices PLL Specifications ⁽¹⁾ (Part 1 of 2)
f_IN ⁽²⁾
f_INPFD
f_VCO ⁽³⁾
f_INDUTY
Symbol
t_{INJITTER_CCJ} ⁽⁴⁾
f_{OUT_EXT} (external clock output)
(2)
Parameter
Input clock frequency
PFD input frequency
PLL internal VCO operating range
Input clock duty cycle
Input clock cycle-to-cycle jitter for F_INPFD  100 MHz
Input clock cycle-to-cycle jitter for F_INPFD < 100 MHz
PLL output frequency
Min Typ Max
Unit
5
— 472.5
MHz
5
—
325
MHz
600
— 1300
MHz
40
—
60
%
—
—
0.15
UI
—
— ±750
ps
—
— 472.5
MHz
f_OUT (to global clock)
t_OUTDUTY
t_LOCK
t_DLOCK
t_{OUTJITTER_PERIOD_DEDCLK} ⁽⁵⁾
t_{OUTJITTER_CCJ_DEDCLK} ⁽⁵⁾
t_{OUTJITTER_PERIOD_IO} ⁽⁵⁾
t_{OUTJITTER_CCJ_IO} ⁽⁵⁾
t_{PLL_PSERR}
t_ARESET
t_CONFIGPLL
PLL output frequency (–6 speed grade)
—
— 472.5
MHz
PLL output frequency (–7 speed grade)
—
—
450
MHz
PLL output frequency (–8 speed grade)
—
— 402.5
MHz
Duty cycle for external clock output (when set to 50%) 45
50
55
%
Time required to lock from end of device configuration —
—
1
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
—
—
1
ms
areset is deasserted)
Dedicated clock output period jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Regular I/O period jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Regular I/O cycle-to-cycle jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Accuracy of PLL phase shift
—
—
300
ps
—
—
30
mUI
—
—
300
ps
—
—
30
mUI
—
—
650
ps
—
—
75
mUI
—
—
650
ps
—
—
75
mUI
—
—
±50
ps
Minimum pulse width on areset signal.
10
—
—
ns
Time required to reconfigure scan chains for PLLs
—
3.5 ⁽⁶⁾
—
SCANCLK
cycles
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2