EP3C80F780C8N Datasheet, PDF (13/34 Pages) Altera Corporation – This chapter describes the electric characteristics, switching characteristics, and I/O timing for Cyclone® III devices. A glossary is also included for your reference.

Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
1–13
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications ⁽¹⁾ (Part 2 of 2)
I/O
Standard
V_CCIO (V)
Min Typ Max
V_ID (mV)
Min Max Min
V_IcM (V) ⁽²⁾
Condition
V_OD (mV) ⁽³⁾
Max Min Typ Max
V_OS (V) ⁽³⁾
Min Typ Max
LVDS
(Column
I/Os)
2.375 2.5 2.625 100
0.05 D_MAX  500 Mbps 1.80
—
0.55
500 Mbps  D_MAX
 700 Mbps
1.80 247
—
600 1.125 1.25 1.375
1.05 D_MAX > 700 Mbps 1.55
BLVDS
(Row I/Os) 2.375 2.5 2.625 100 — —
—
— —— — — — —
(5)
BLVDS
(Column 2.375 2.5 2.625 100 — —
—
— —— — — — —
I/Os) ⁽⁵⁾
mini-LVDS
(Row I/Os) 2.375 2.5 2.625 — — —
—
— 300 — 600 1.0 1.2 1.4
(6)
mini-LVDS
(Column 2.375 2.5 2.625 — — —
—
— 300 — 600 1.0 1.2 1.4
I/Os) ⁽⁶⁾
RSDS^®
(Row
2.375 2.5 2.625 — — —
—
— 100 200 600 0.5 1.2 1.5
I/Os) ⁽⁶⁾
RSDS
(Column 2.375 2.5 2.625 — — —
—
— 100 200 600 0.5 1.2 1.5
I/Os) ⁽⁶⁾
PPDS^®
(Row I/Os) 2.375 2.5 2.625 — — —
—
— 100 200 600 0.5 1.2 1.4
(6)
PPDS
(Column 2.375 2.5 2.625 — — —
—
— 100 200 600 0.5 1.2 1.4
I/Os) ⁽⁶⁾
Notes to Table 1–18:
(1) For an explanation of terms used in Table 1–18, refer to “Transmitter Output Waveform” in “Glossary” on page 1–27.
(2) V_IN range: 0 V  V_IN  1.85 V.
(3) R_L range: 90  R_L  110  .
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.
(5) No fixed V_IN, V_OD, and V_OS specifications for BLVDS. They are dependent on the system topology.
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2