5AGXFB7K4F40I3N Datasheet, PDF (13/39 Pages) Altera Corporation – Key Advantages of Arria V Devices

AV-51001
2013.12.26
Resource
HPS I/O
LVDS
Transmitter
Receiver
PCIe Hard IP Block
FPGA Hard Memory Controller
HPS Hard Memory Controller
ARM Cortex-A9 MPCore Processor
Package Plan
13
B3
208
120
136
2
3
1
Dual-core
Member Code
B5
208
120
136
2
3
1
Dual-core
Related Information
High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook
Provides the number of LVDS channels in each device package.
Package Plan
Table 11: Package Plan for Arria V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O
pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
F896
F1152
F1517
Member Code
FPGA
GPIO
(31 mm)
HPS I/O
XCVR
FPGA
GPIO
(35 mm)
HPS I/O
XCVR
FPGA
GPIO
(40 mm)
HPS I/O
XCVR
B3
250
208
12
385
208
18
540
208
30
B5
250
208
12
385
208
18
540
208
30
Arria V ST
This section provides the available options, maximum resource counts, and package plan for the Arria V ST
devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Altera Product Selector
Provides the latest information about Altera products.
Arria V Device Overview
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