EP5388QI Datasheet, PDF (11/13 Pages) Enpirion, Inc. – 800mA Synchronous Buck Regulator With Integrated Inductor 3mm x 3mm x 1.1mm Package

A single 10uF 0805 MLCC can be used if V_OUT
programming is accomplished using an
external divider, with the addition of a 10pF
phase lead capacitor as shown in Figure 5.
Note that in this configuration, V_SENSE should
NOT be connected to V_OUT.
As described in the Soft Start section, there is
a limitation on the maximum bulk capacitance
that can be placed on the output of this device.
Please refer to that section for more details.
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
equivalent dielectric formulations lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-
Layout Considerations*
*Optimized PCB layout file is downloadable from the
Altera website to assure first pass design success.
Refer to figure 6 for the following layout
recommendations.
Recommendation 1: The input and output
filter capacitors should be placed as close to
the EP5388QI as possible to reduce EMI from
input and output loop AC currents. This
reduces the physical area of these AC current
loops.
Recommendation 2: The system ground
plane should be the first layer immediately
below the surface layer (PCB layer 2). If it is
not possible to make PCB layer 2 the system
ground plane, a local ground island should be
created on PCB layer 2 under the Altera
Enpirion device and including the area under
the input and output filter capacitors. This
ground plane, or ground island, should be
continuous and uninterrupted underneath the
Altera Enpirion device and the input and output
filter capacitors.
Recommendation 3: The surface layer
ground pour should include a “slit” as shown in
EP5388QI
mode DC-DC converter output filter
applications.
V_IN
4.7uF
0603
ENABLE
V_in
V_Sense
V_out
EP5388QI ^Ra
VS0
VFB
VS1
Rb
VS2
GND
V_OUT
10µF
0805
10pF
Figure 5. Applications circuit for C_OUT = 1 x 10uF 0805.
figure 6 to separate the input and output AC
loop currents. This will help reduce noise
coupling from the input current loop to the
output current loop.
Recommendation 4: Multiple small vias
(approximately 0.25mm finished diameter)
should be used to connect the ground
terminals of the input and output capacitors,
and the surface ground pour under the device,
to the system ground plane. If a local ground
island is used on PCB layer 2, the vias should
connect to the ground island and continue
down to the PCB system ground plane.
Recommendation 5: The AGND pin should
be connected to the system ground plane
using a via as described in recommendation 4.
AGND must NOT be connected to the surface
layer ground pour.
Recommendation 6: As with any switch-
mode DC-DC converter, do not run any
sensitive signal or control lines under the
converter package.
02377
October 11, 2013
www.altera.com/enpirion Page 11
Rev D