EP5388QI Datasheet, PDF (10/13 Pages) Enpirion, Inc. – 800mA Synchronous Buck Regulator With Integrated Inductor 3mm x 3mm x 1.1mm Package

EP5388QI
defined as V_LOW ≤ 0.4V. Logic high is defined
as V_HIGH ≥ 1.4V. Any level between these two
values is indeterminate. These pins must not
be left floating.
Table 1. VID voltage select settings.
VS2
VS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
VS0
0
1
0
1
0
1
0
1
V_OUT
3.3V
2.5V
1.8V
1.5V
1.25V
1.2V
0.8V
User
Selectable
External Voltage Divider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to VIN or logic “high”.
The EP5388QI uses a separate feedback pin,
V_FB, when using the external divider. VSENSE
must be connected to V_OUT as indicated in
Figure 4.
V_IN
4.7uF
0603
ENABLE
V_in
V_Sense
V_out
EP5388QI ^Ra
VS0
VFB
VS1
Rb
VS2
GND
V_OUT
47µF
1206
Figure 4. External Divider application circuit.
The output voltage is selected by the following
formula:
( ) V_OUT
= 0.603V
1+
Ra
Rb
R_a must be chosen as 200KΩ to maintain loop
gain. Then R_b is given as:
R ^{= 1.206x105 Ω}
b _{VOUT − 0.603}
V_OUT can be programmed over the range of
0.6V to V_IN-0.5V.
Dynamically Adjustable Output
The EP5388QI is designed to allow for
dynamic switching between the predefined VID
voltage levels. The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
transition. The slew rate is identical to the soft-
start slew rate of 1.5V/mS.
Dynamic transitioning between internal VID
settings and the external divider is not allowed.
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before VIN. During power down, the
VIN should not be powered down before the
ENABLE. Tying PVIN and ENABLE together
during power-up or power-down meets this
requirement.
Pre-Bias Start-up
The EP5388QI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5388QI is not pre-biased when the
EP5388QI is first enabled.
Input and Output Capacitors
The input capacitance requirement is 4.7uF
0603 MLCC. Altera recommends that a low
ESR MLCC capacitor be used. The input
capacitor must use a X5R or X7R or equivalent
dielectric formulation. Y5V or equivalent
dielectric formulations lose capacitance with
frequency, bias, and with temperature, and are
not suitable for switch-mode DC-DC converter
input filter applications.
A variety of output capacitor configurations are
possible depending on footprint and ripple
requirements. For applications where V_IN
range is up to 5.5V, it is recommended to use a
single 47uF 1206 MLCC capacitor. Ripple
performance can be improved by using 2 x
22uF 0805 MLCC capacitors.
02377
October 11, 2013
www.altera.com/enpirion Page 10
Rev D