EPM7032LC44-7 Datasheet, PDF (1/66 Pages) Altera Corporation – Programmable Logic Device Family

®
September 2005, ver. 6.7
MAX 7000
Programmable Logic
Device Family
Data Sheet
Features...
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■ High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX^® architecture
■ 5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
■ PCI-compliant devices available
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Features
Feature EPM7032
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t_PD (ns)
t_SU (ns)
t_FSU (ns)
t_CO1 (ns)
f_CNT (MHz)
600
32
2
36
6
5
2.5
4
151.5
EPM7064
1,250
64
4
68
6
5
2.5
4
151.5
EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
1,800
2,500
3,200
3,750
5,000
96
128
160
192
256
6
8
10
12
16
76
100
104
124
164
7.5
7.5
10
12
12
6
6
7
7
7
3
3
3
3
3
4.5
4.5
5
6
6
125.0
125.0
100.0
90.9
90.9
Altera Corporation
1
DS-MAX7000-6.7