EP1M120 Datasheet, PDF (1/86 Pages) Altera Corporation – Programmable Logic Device Family

®
January 2003, ver. 2.2
Mercury
Programmable Logic
Device Family
Data Sheet
Features…
■ High-performance programmable logic device (PLD) family (see
Table 1)
– Integrated high-speed transceivers with support for clock data
recovery (CDR) at up to 1.25 gigabits per second (Gbps)
– Look-up table (LUT)-based architecture optimized for high
speed
– Advanced interconnect structure for fast routing of critical paths
– Enhanced I/O structure for versatile standards and interface
support
– Up to 14,400 logic elements (LEs)
■ System-level features
– Up to four general-purpose phase-locked loops (PLLs) with
programmable multiplication and delay shifting
– Up to 12 PLL output ports
– Dedicated multiplier circuitry for high-speed implementation of
signed or unsigned multiplication up to 16 × 16
– Embedded system blocks (ESBs) used to implement memory
functions including quad-port RAM, true dual-port RAM, first-
in first-out (FIFO) buffers, and content-addressable memory
(CAM)
– Each ESB contains 4,096 bits and can be split and used as two
2,048-bit unidirectional dual-port RAM blocks
Table 1. Mercury Device Features
Feature
Typical gates
HSDI channels
LEs
ESBs (1)
Maximum RAM bits
Maximum user I/O pins
EP1M120
120,000
8
4,800
12
49,152
303
EP1M350
350,000
18
14,400
28
114,688
486
Note to Table 1:
(1) Each ESB can be used for two dual- or single-port RAM blocks.
13
Altera Corporation
1
DS-MERCURY-2.2