4GB-DDR3L-AS4C256M16D3L Datasheet, PDF (72/89 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

4Gb DDR3L -AS4C256M16D3L
Figure 40. Write Timing Definition and parameters
T0
T1
T2
T3
T4
T5
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank
Col n
DQS, DQS#
t_DQSS(min)
WL = AL + CWL
tWPRE(min) ^{tDQSS tDSH}
T6
T7
NOP
NOP
tDSH
tDSH
T8
T9
NOP
NOP
tDSH t_WPST(min)
Notes 2
DQ
tDQSH(min) t_DQSL
tDSS
tDQSH
Din
n
tDQSL t_DQSH
tDSS
tDQSL tDQSH
tDSS
Din
Din
Din
n+2
n+3
n+4
tDQSL t_DQSH
tDSS
tDQSL(min)
tDSS
Din
Din
n+6
n+7
T10
NOP
DM
t_{DQSS(nominal)}
DQS, DQS#
Notes 2
DQ
DM
t_DQSS(max)
DQS, DQS#
Notes 2
DQ
DM
tWPRE(min)
tDSH
tDSH
tDSH
tDSH
tWPST(min)
tDQSH(min) t_DQSL
tDSS
tDQSH
Din
n
tDQSL
tDSS
tDQSH
tDQSL
tDSS
tDQSH
Din
Din
Din
n+2
n+3
n+4
tDQSL
tDSS
tDQSH tDQSL(min)
tDSS
Din
Din
n+6
n+7
tDQSS
tDSH
tWPRE(min)
tDSH
tDSH
tDSH
tWPST(min)
tDQSH(min) t_DQSL
tDQSH tDQSL
tDQSH tDQSL
tDQSH tDQSL
tDQSH tDQSL(min)
tDSS
tDSS
tDSS
tDSS
tDSS
Din
Din
Din
Din
Din
Din
n
n+2
n+3
n+4
n+6
n+7
NOTES:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
TRANSITIONING DATA
Don't Care
Confidential
72
Rev. 2.0
Aug. /2014