4GB-DDR3L-AS4C256M16D3L Datasheet, PDF (1/89 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

4Gb DDR3L – AS4C256M16D3L
Revision History
AS4C256M16D3L - 96-ball FBGA PACKAGE
Revision
Rev 1.0
Rev 2.0
Details
Preliminary datasheet
Added "Backward compatible to VDD & VDDQ = 1.5V +/-
0.075V" - page 2
Added CL=5 & CL=6 to Table 18 – page 31
Updated Table 12. Recommended DC Operating
Conditions – page 26
Date
April 2014
August 2014
Confidential
1
Rev. 2.0
Aug. /2014