2GB-DDR3L-AS4C256M8D3L Datasheet, PDF (69/86 Pages) Alliance Semiconductor Corporation – Bidirectional differential data strobe

2Gb DDR3L - AS4C256M8D3L
Figure 41. WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8)
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank,
Col n
WL = AL + CWL
DQS, DQS#
t_WPRE
T8
T9
NOP
NOP
t_WPST
Notes 2
DQ
Din
Din
Din
Din
Din
Din
Din
Din
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
NOTES:
1. BL8, WL = 5; AL = 0, CWL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
TRANSITIONING DATA
T10
NOP
Don't Care
Figure 42. WRITE Burst Operation WL = 9 (AL = CL-1, CWL = 5, BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
DQS, DQS#
Notes 2
DQ
Bank,
Col n
t_WPRE
AL = 4
WL = AL + CWL
CWL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. BL8, WL = 9; AL = (CL - 1), CL = 5, CWL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
TRANSITIONING DATA
Don't Care
Confidential
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Rev. 2.0
Aug. /2014