2GB-DDR3L-AS4C256M8D3L Datasheet, PDF (18/86 Pages) Alliance Semiconductor Corporation – Bidirectional differential data strobe

2Gb DDR3L - AS4C256M8D3L
 Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write
latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0
and BA2, while controlling the states of address pins according to the table below.
Table 8. Extended Mode Register EMR (2) Bitmap
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0^*1 1
0
0^*1
Rtt_WR 0^*1 SRT ASR
CWL
PASR
Mode Register (2)
BA1 BA0 MRS mode
00
MR0
01
MR1
10
MR2
11
MR3
A6 Auto Self-Refresh (ASR)
0 Manual SR Reference (SRT)
1
ASR enable (Optional)
A10 A9
RTT_WR ^*2
0 0 Dynamic ODT off (Write does not affect Rtt value)
01
10
11
RZQ/4
RZQ/2
Reserved
A2 A1 A0 Partial Array Self-Refresh (Optional)
000
Full Array
001
HalfArray (BA[2:0]=000,001,010,&011)
010
011
Quarter Array (BA[2:0]=000,&001)
1/8^th Array (BA[2:0]=000)
1 0 0 3/4 Array (BA[2:0]=010,011,100.101,110,&111)
101
HalfArray (BA[2:0]=100,101,110,&111)
110
111
Quarter Array (BA[2:0]=110,&111)
1/8^th Array (BA[2:0]=111)
A7 ^{Self-Refresh Temperature (SRT) Range}
0
Normal operating temperature range
1 Extended (optional) operating temperature range
A5 A4 A3
000
001
010
011
100
101
110
111
CAS write Latency (CWL)
5 (tCK(avg)≧2.5ns)
6 (2.5ns＞tCK(avg)≧1.875ns)
7 (1.875ns＞tCK(avg)≧1.5ns)
8 (1.5ns＞tCK(avg)≧1.25ns)
Reserved
Reserved
Reserved
Reserved
Note 1: BA2 and A8, A11~ A14 are RFU and must be programmed to 0 during MRS.
Note 2: The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
Confidential
18
Rev. 2.0
Aug. /2014