AS7C3513 Datasheet, PDF (6/8 Pages) Alliance Semiconductor Corporation – 5V/3.3V 32K x 6 CMOS SRAM

Parameter
V_CC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
Symbol
V_DR
I_CCDR
t_CDR
t_R
| I_LI |
Test conditions
Min
Max
Unit
2.0
V_CC = 2.0V
–
CE ≥ V_CC–0.2V
0
V_IN ≥ V_CC–0.2V or
V_IN ≤ 0.2V
t_RC
–
–
V
500
µA
–
ns
–
ns
1
µA
Data retention mode
V_CC
V_CC
V_DR ≥ 2.0V
V_CC
t_CDR
t_R
CE
V_IH
V_DR
V_IH
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Ω
Ω
Ω
Ω
Ω
1 During V_CC power-up, a pull-up resistor to V_CC on CE is required to meet I_SB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4 These parameters are specified with C_L = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to the commercial operating range only.
14 C=30pF, except on High Z and Low Z parameters, where C=5pF.