AS7C256B Datasheet, PDF (6/8 Pages) Alliance Semiconductor Corporation – 5V 32K X 8 CMOS SRAM (Common I/O)

AS7C256B
®
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to V_CC. See Figure A.
- Input rise and fall times: 3 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
V_CC
90%
90%
10%
GND
3 ns
10%
Figure A: Input pulse
Thevenin equivalent
168Ω
D_out
+1.72V (5V)
V_CC
D_out
255Ω
480Ω
C⁽¹³⁾
GND
Figure B: Output load
Notes
1 During V_CC power-up, a pull-up resistor to V_CC on CE is required to meet I_SB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±200mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
12/5/06; V.1.0
Alliance Memory
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