AS7C256B Datasheet, PDF (1/8 Pages) Alliance Semiconductor Corporation – 5V 32K X 8 CMOS SRAM (Common I/O)

September 2006
Advance Information
AS7C256B
®
5V 32K X 8 CMOS SRAM (Common I/O)
Features
• Industrial (-40^o to 85^oC) temperature
• Organization: 32,768 words × 8 bits
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• One chip select plus one Output Enable pin
• Bidirectional data inputs and outputs
• TTL-compatible
• 28-pin JEDEC standard packages
- 300 mil SOJ
- 8 × 13.4 mm TSOP
- 300 mil PDIP
• ESD protection ≥ 2000 volts
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
Input buffer
32,768 X 8
Array
(262,144)
Address decoder
AAAAAAA
8 9 10 11 12 13 14
Control
circuit
Pin arrangement
28-pin DIP, SOJ (300 mil)
I/O7
I/O0
WE
OE
CE
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O0
11
I/O1
12
I/O2
13
GND
14
28
V_CC
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE
19
I/O7
18
I/O6
17
I/O5
16
I/O4
15
I/O3
28-pin TSOP 1 (8×13.4mm)
OE 1 (22)
(21) 28
A11 2 (23)
(20) 27
A9 3 (24)
(19) 26
A8 4 (25)
(18) 25
A13 5 (26)
(17) 24
WE 6 (27)
(16) 23
V_CC
A14
7
8
(28) _AS7C256B (15) 22
(1)
(14) 21
A12 9 (2)
(13) 20
A7 10 (3)
(12) 19
A6 11 (4)
(11) 18
A5 12 (5)
(10) 17
A4 13 ⁽⁶⁾
(9) 16
A3 14 ⁽⁷⁾
(8) 15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
12/5/06; V.1.0
Alliance Memory
P. 1 of 8
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