8MX16-DDR1-AS4C8M16D1A Datasheet, PDF (52/66 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

 
8Mx16 DDR1-AS4C8M16D1A
F  igure 29. Power-Down
CK
CK
CKE
T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6
t_IS
t_IS
COMMAND
VALID
NOP
NOP
VALID
No column access
in progress
Enter power-down
mode
Exit power-down
mode
Figure 30. Clock Frequency Change in Precharge
Don’t Care
CK
CK
CMD
CKE
T0
T1
T2
T4
Tx Tx+1
NOP NOP
Frequency Change
Occurs here
t_RP
Minmum 2 clocks
Required before
Changing frequency
Ty Ty+1 Ty+2 Ty+3 Ty+4
Tz
NOP
t_IS
DLL
RESET
NOP
NOP
Valid
Stable new clock
Before power down
exit
200 Clocks
Confidential
- 52/66 -
Rev.1.1 July 2015