8MX16-DDR1-AS4C8M16D1A Datasheet, PDF (36/66 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

 
8Mx16 DDR1-AS4C8M16D1A
R  ead to Precharge Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
DQS
DQ
READ
Bank A,
Col n
NOP
PRE
CL=2.5
Bank
(a or all)
NOP
t_RP
NOP
ACT
Bank A,
Row
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
- 36/66 -
Rev.1.1 July 2015