AS4C64M16D2-25BAN Datasheet, PDF (51/59 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C64M16D2-25BAN
Figure 40. Burst read operation with auto precharge followed by an activation to the same
bank (t_RP Limit): (RL=5 (AL=2, CL=3, internal t_RCD=3, BL=4, t_RTP≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
A10= 1
CMD
DQS
DQS#
DQ's
Post CAS#
READ A
NOP
NOP
>=t_RAS(min)
NOP
NOP
NOP
Auto Precharge Begins
NOP
Bank A
Activate
AL= 2
CL= 3
RL= 5
>= t_RC
>= t_RP
DoutA0 DoutA1 DoutA2 DoutA3
CL=3
T8
NOP
Figure 41. Burst write with auto-precharge (t_RC Limit): WL=2, WR=2, BL=4, t_RP=3
T0
T1
CK#
CK
A10 = 1
CMD
Post CAS#
WRA Bank A
NOP
DQS
DQS#
WL= RL-1=2
DQ's
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
Auto Precharge Begins
>=WR
>=t_RP
DNA₀ DNA₁ DNA₂ DNA₃
>=t_RC
Tm
Bank A
Active
Confidential
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Rev.1.0 Dec 2015