AS4C64M16D2-25BAN Datasheet, PDF (46/59 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C64M16D2-25BAN
Figure 30. Burst read operation followed by precharge:
(RL=4, AL=1, CL=3, BL=4, t_RTP ≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
CMD
DQS
DQS#
DQ
Post CAS#
Read A
NOP
AL+BL'/2 clks
NOP
Precharge
AL=1
CL=3
RL=4
>=t_RAS
>=t_RTP
NOP
NOP
NOP
>=t_RP
DOUTA0 DOUTA1 DOUTA2 DOUTA3
CL=3
Bank A
Active
NOP
Figure 31. Burst read operation followed by precharge:
(RL=4, AL=1, CL=3, BL=8, t_RTP≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
CMD Post CAS#
READ A
NOP
DQS
AL + BL/2 clks
DQS#
AL = 1
NOP
CL = 3
DQ's
RL= 4
NOP
NOP
Precharge A
NOP
NOP
NOP
DOUT
A0
>=t_RTP
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
A4
DOUT
A5
DOUT
A6
DOUT
A7
First 4-bit prefetch
Second 4-bit prefetch
Confidential
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Rev.1.0 Dec 2015