AS4C128M16D3LA-12BIN Datasheet, PDF (51/83 Pages) Alliance Semiconductor Corporation – 96 ball FBGA PACKAGE

AS4C128M16D3LA-12BIN
z Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a
transition period around power down entry, where the DDR3L SDRAM may show either synchronous or
asynchronous ODT behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is
counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the
clock cycle where CKE is first registered low. The transition period begins with the starting point of tANPD and
terminates at the end point of tCPDED(min). If there is a Refresh command in progress while CKE goes low, then
the transition period ends at the later one of tRFC(min) after the Refresh command and the end point of
tCPDED(min). Please note that the actual starting point at tANPD is excluded from the transition period, and the
actual end point at tCPDED(min) and tRFC(min, respectively, are included in the transition period.
ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and
(ODTLon*tck+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion
during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and
(ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL
has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three
different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition
period; ODT_C shows a state change after the transition period.
z Asynchronous to Synchronous ODT Mode transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also
a transition period around power down exit, where either synchronous or asynchronous response to a change in
ODT must be expected from the DDR3L SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered
high. tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and
(ODTLon* tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-
assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and
(ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has
a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different
cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition
period; ODT_A shows a state change of ODT after the transition period with synchronous response.
z Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD
exit may overlap. In this case, the response of the DDR3L SDRAMs RTT to a change in ODT state at the input may
be synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition
period (even if the entry ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case,
the response of the DDR3L SDRAMs RTT to a change in ODT state at the input may be synchronous or
asynchronous from the state of the PD exit transition period to the end of the PD entry transition period. Note that in
the following figure, it is assumed that there was no Refresh command in progress when Idle state was entered.
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Rev. 1.0 May 2016