AS4C128M16D3LA-12BIN Datasheet, PDF (12/83 Pages) Alliance Semiconductor Corporation – 96 ball FBGA PACKAGE

AS4C128M16D3LA-12BIN
Register Definition
z Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers,
provided by the DDR3L SDRAM, as user defined variables and they must be programmed via a Mode Register Set
(MRS) command. As the default values of the Mode Registers are not defined, contents of Mode Registers must be
fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation. Also the contents of
the Mode Registers can be altered by re-executing the MRS command during normal operation. When
programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address
fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and
DLL Reset do not affect array contents, which mean these commands can be executed any time after power-up
without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register
and is the minimum time required between two MRS commands shown in Figure of tMRD timing.
Figure 6. tMRD timing
T0
T1
T2
CK#
CK
COMMAND ^VALID
VALID
VALID
ADDRESS
VALID
VALID
VALID
CKE
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
MRS
VALID
NOP/DES
NOP/DES
VALID
VALID
MRS
VALID
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
Tc2
VALID
VALID
Settings
Old Settings
ODT
ODT
RTT_Nom ENABLED prior and/or after MRS command
VALID
VALID
ODTLoff + 1
RTT_Nom DISABLED prior and after MRS command
VALID
VALID
VALID
VALID
t_MRD
Updating Settings
t_MOD
VALID
VALID
VALID
VALID
VALID
New Settings
VALID
VALID
VALID
TIME BREAK
Don't Care
Confidential
-1283-
Rev. 1.0 May 2016