AS6C2008 Datasheet, PDF (5/13 Pages) Alliance Semiconductor Corporation – 256K X 8 BIT LOW POWER CMOS SRAM

February 2007
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Address
Dout
tRC
tAA
Previous Data Valid
AS6C2008
®
256K X 8 BIT LOW POWER CMOS SRAM
tOH
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
Address
CE#
CE2
tRC
tAA
tACE
OE#
Dout
High-Z
tOE
tOLZ
tCLZ
tOH
tOHZ
tCHZ
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
10/February/07, v.1.0
Alliance Memory Inc.
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