16MX16-DDR1-AS4C16M16D1A Datasheet, PDF (47/64 Pages) Alliance Semiconductor Corporation – Auto Refresh and Self Refresh

 
16Mx16 DDR1-AS4C16M16D1A
F  igure 25. Write to Precharge Max tDQSS, Interrupting
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK
CK
COMMAND
ADDRESS
DQS
WRITE
NOP
Bank a,
Col n
tDQSS (max)
NOP
NOP
tWR
NOP
*2
PRE
Bank
(a or all)
tRP
DQ
DI
n
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 2 data elements are written
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
DM= UDM & LDM
Don’t Care
Confidential
- 47/64 -
Rev.1.1 July 2015