AS7C33512PFD18A Datasheet, PDF (4/20 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 18 pipeline burst synchronous SRAM

AS7C33512PFD18A
®
Functional description
The AS7C33512PFD18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) devices organized as
524,288 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.
Fast cycle times of 6/7.5 ns with clock access times (t_CD) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Three chip enable inputs
permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and
driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on
all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address
strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium^®1
count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC^™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW. This device operates in double-cycle deselect feature during
read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33512PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are
available in a 100-pin 14×20 mm TQFP packaging.
.
Capacitance
Parameter
Input capacitance
I/O capacitance
*Guaranteed _{not tested}
Symbol
C_IN*
C_I/O*
Test conditions
V_IN = 0V
V_IN = V_OUT = 0V
Max
Unit
5
pF
7
pF
TQFP thermal resistance
Description
Conditions
Thermal resistance
(junction to ambient)¹
Thermal resistance
(junction to top of case)¹
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
1 This parameter is sampled.
1–layer
4–layer
Symbol
θ_JA
θ_JA
θ_JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
1. PowerPC^™ is a trademark International Business Machines Corporation
12/1/04; v.1.3
Alliance Semiconductor
4 of 20