AS7C33512PFD18A Datasheet, PDF (1/20 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 18 pipeline burst synchronous SRAM

November 2004
AS7C33512PFD18A
®
3.3V 512K × 18 pipeline burst synchronous SRAM
Features
• Organization: 524,288 words × 18 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Asynchronous output enable control
• Individual byte write and global write
• Available in 100-pin TQFP package
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
Logic block diagram
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
19
Power
down
LBO
CLK
CS _{Burst logic}
CLR
D
Q ¹⁹
CS
Address
register
CLK
17 19
512K × 18
Memory
array
18
18
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
–166
6
166
3.5
475
130
30
12/1/04; v.1.3
Alliance Semiconductor
–133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
1 of 20
Copyright © Alliance Semiconductor. All rights reserved.