AS4C4M16SA Datasheet, PDF (39/54 Pages) Alliance Semiconductor Corporation – Synchronous DRAM

AS4C4M16SA - Automotive
Figure 32.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
CLK
CKE
CS#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
RAx
RAx
tRCD
DQ
Hi-Z
Activate
Command
Bank A
RBx
CAx RBx
CBx
CBy
CBz
CAy
tAC
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Precharge
Command
Bank B
Precharge
Command
Bank A
Don’t Care
Confidential
39
Rev. 1.0-63nm Mar. /2014