AS4C32M16SM Datasheet, PDF (38/73 Pages) Alliance Semiconductor Corporation – PC133-compliant

Figure 16: Random READ Accesses
AS4C32M16SM
Data from any READ burst can be truncated with a subsequent WRITE command, and data
from a fixed-length READ burst can be followed immediately by data from a WRITE
command (subject to bus turnaround limitations). The WRITE burst can be initiated on the
clock edge immediately following the last (or last desired) data element from the READ burst,
provided that I/O contention can be avoided. In a given system design, there is a possibility
that the device driving the input data will go Low-Z before the DQ go High-Z. In this case, at
least a single-cycle delay should occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 17 (page 44) and Figure
18 (page 45). The DQM signal must be asserted (HIGH) at least two clocks prior to the
WRITE command (DQM latency is two clocks for output buffers) to suppress da-ta-out from
the READ. After the WRITE command is registered, the DQ will go to High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4, then the
WRITEs at T5 and T7 would be valid, and the WRITE at T6 would be invalid.
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Rev1.0, July 2014