AS4C32M16SM Datasheet, PDF (22/73 Pages) Alliance Semiconductor Corporation – PC133-compliant

REFRESH
AUTO REFRESH
SELF REFRESH
AS4C32M16SM
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-
BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. All active banks must be pre-charged prior to
issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued
t
until the minimum RP has been met after the PRECHARGE command, as shown in
Bank/Row Activation (page 40).
The addressing is generated by the internal refresh controller. This makes the address bits a
“Don’t Care” during an AUTO REFRESH command. Regardless of device width, the 512Mb
SDRAM requires 8192 AUTO REFRESH cycles every 64ms (commercial and industrial).
Providing a distributed AUTO REFRESH command every 7.813μ s (commercial and
industrial) will meet the refresh requirement and ensure that each row is refreshed.
Alternative_tly, 8192 AUTO REFRESH commands can be issued in a burst at the minimum
cycle rate ( RFC), once every 64ms (commercial and industrial).
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of
the system is powered-down. When in the self-refresh mode, the SDRAM retains data without
external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE
is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the
SDRAM become a “Don’t Care” with the exception of CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it
to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-fresh mode
t
for a minimum period equal to RAS and may remain in self refresh mode for an indefinite
period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP
t
commands issued (a minimum of two clocks) for XSR because time is required for the
completion of any internal refresh in progress.
Upon exiting the self-refresh mode, AUTO REFRESH commands must be issued at the
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Confidential
22 | P a g e
Rev1.0, July 2014