2GB-DDR2-AS4C256M8D2 Datasheet, PDF (38/70 Pages) Alliance Semiconductor Corporation – Weak Strength Data-Output Driver Option

2Gb DDR2 - AS4C256M8D2
B urs t Write with A uto-P rec harge
If A10 is high when a Write C ommand is is s ued, the W rite with Auto-P recharge function is engaged. T he
DDR 2 S DR AM automa tically begins precharge operation after the completion of the write burst plus the
write recovery time delay (W R ), programmed in the MR S regis ter, as long a s tR AS is s atis fied. T he bank
undergoing Auto-P recharge from the completion of the write burst may be reactiva ted if the following two con-
ditions are s atis fied.
(1) T he las t data-in to bank a ctivate delay time (tDAL = W R + tR P ) has been s atis fied.
(2) T he R AS cycle time (tR C ) from the previous bank activation has been s atis fied.
In DDR 2 S DR AMs the write recovery time delay (W R ) has to be programmed into the MR S mode regis ter.
As long as the analog tW R timing parameter is not violated, W R can be programmed between 2 and 6 clock
cycles. Minimum W rite to Activate comma nd s pacing to the s ame bank = W L + B L /2 + tDA L .
E xamples :
B urs t Write with A uto-P rec harge (tR C L imit) : W L = 2, tDA L = 6 (WR = 3, tR P = 3) , B L = 4
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
C MD
DQS ,
DQS
DQ
WR ITE A
NOP
NOP
A10 ="high"
NOP
NOP
NOP
C ompletion of the B urst W rite
NOP
NOP
B ank A
A ctiva te
Auto-P recharge B egins
W L = R L-1 = 2
DIN A0 DIN A1 DIN A2 DIN A3
WR
tDAL
tR C min.
>=tR AS min.
tR P
B W -AP223
Confidential
-38/70-
Rev.1.0 Sep. 2015