AS4C128M8D1-6TIN Datasheet, PDF (33/57 Pages) Alliance Semiconductor Corporation – Concurrent auto precharge option is supported

AS4C128M8D1-6TIN
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1: Operating current: One bank operation
1. _{Typical Case: VDD = 2.5V, T=25} ^o_{C for DDR333;}
2. Worst Case: VDD = 2.7V, T= 0 ^oC
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR266 (133 Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
Read: A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
IDD7: Operating current: F our bank operation
1. _{Typical Case: VDD = 2.5V, T=25} ^o_{C for DDR333;}
2. Worst Case: VDD = 2.7V, T= 0 ^oC
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR266 (133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Confidential
- 33 of 57 -
Rev. 1.0 Dec. 2016