ASM5I9772A Datasheet, PDF (3/15 Pages) Alliance Semiconductor Corporation – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

June 2005
ASM5I9772A
rev 0.3
Pin Description¹
Pin
Name
I/O
Type
Description
11
XIN
I
Analog
Crystal oscillator input.
12
XOUT
O Analog
Crystal oscillator output.
9
TCLK0
I, PU LVCMOS LVCMOS/LVTTL reference clock input.
10
TCLK1
I, PU LVCMOS LVCMOS/LVTTL reference clock input.
44, 46, 48, 50 QA(3:0)
O LVCMOS Clock output bank A.
32, 34, 36, 38 QB(3:0)
O LVCMOS Clock output bank B.
16, 18, 21, 23 QC(3:0)
29
FB_OUT
31
FB_IN
O
O
I, PU
LVCMOS
LVCMOS
LVCMOS
Clock output bank C.
Feedback clock output. Connect to FB_IN for normal
operation.
Feedback clock input. Connect to FB_OUT for normal
operation. This input should be at the same voltage rail as input
reference clock. See Table 1.
25
SYNC
O
LVCMOS
Synchronous pulse output. This output is used for system
synchronization.
PLL enable/bypass input. When Low, PLL is
6
PLL_EN
I, PU LVCMOS disabled/bypassed and the input clock connects to the output
dividers.
2
MR#/OE
I, PU LVCMOS Master reset and Output enable/disable input. See Table 2
8
TCLK_SEL
I, PU LVCMOS LVCMOS Clock reference select input. See Table 2.
7
REF_SEL
I, PU LVCMOS LVCMOS/LVPECL Reference select input. See Table 2.
52
VCO_SEL
I, PU LVCMOS VCO Operating frequency select input. See Table 2.
14
INV_CLK
I, PU LVCMOS QC(2,3) Phase selection input. See Table 2.
5, 26, 27
FB_SEL(2:0) I, PU LVCMOS Feedback divider select input. See Table 6.
42, 43
SELA(1,0)
I, PU LVCMOS Frequency select input, Bank A. See Table 3.
40, 41
SELB(1,0)
I, PU LVCMOS Frequency select input, Bank B. See Table 4.
19, 20
SELC(1,0)
I, PU LVCMOS Frequency select input, Bank C. See Table 5.
3
SCLK
I, PU LVCMOS Serial Clock input.
4
45, 49
33, 37
22, 17
13
28
SDATA
VDDQA
VDDQB
VDDQC
AVDD
VDD
I, PU
Supply
Supply
Supply
Supply
Supply
LVCMOS
VDD
VDD
VDD
VDD
VDD
Serial Data input.
2.5V or 3.3V Power supply for bank A output clocks^2,3.
2.5V or 3.3V Power supply for bank B output clocks.^2,3
2.5V or 3.3V Power supply for bank C output clocks. ^2,3
2.5V or 3.3V Power supply for PLL. ^2,3
2.5V or 3.3V Power supply for core and inputs.^2,3
1
AVSS
Supply Ground
Analog Ground.
15, 24, 30,
35, 39, 47, 51
VSS
Supply Ground
Common Ground.
Note: 1.PU = Internal pull up, PD = Internal pull down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3 AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power
supply pins.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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