ASM5I9772A Datasheet, PDF (1/15 Pages) Alliance Semiconductor Corporation – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

June 2005
ASM5I9772A
rev 0.3
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
ƒ Output frequency range: 8.33 MHz to 200 MHz
ƒ Input frequency range: 6.25 MHz to 125 MHz
ƒ 2.5V or 3.3V operation
ƒ Split 2.5V/3.3V outputs
ƒ ±2% max Output duty cycle variation
ƒ 12 clock outputs: drive up to 24 clock lines
ƒ One feedback output
ƒ Three reference clock inputs: crystal or LVCMOS
ƒ 300pS max output-output skew
ƒ Phase-locked loop (PLL) bypass mode
ƒ ‘SpreadTrak’
ƒ Output enable/disable
ƒ Pin-compatible with CY29772, MPC9772 and MPC972
ƒ Industrial temperature range: –40°C to +85°C
ƒ 52 pin 1.0 mm TQFP package
ƒ RoHS Compliance
Functional Description
The ASM5I9772A is a low-voltage high-performance
200 MHz PLL-based zero delay buffer, designed for high-
speed clock-distribution applications.
The ASM5I9772A features one on-chip crystal oscillator
and two LVCMOS reference clock inputs and provides 12
outputs partitioned in three banks of four outputs each.
Each bank divides the VCO output per SEL(A:C) settings,
see Functional Table.
These dividers allow output to input ratios of 8:1, 6:1, 5:1,
4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50Ω series or
parallel-terminated transmission lines. For series-
terminated transmission lines, each output can drive one or
two traces, giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz and 500 MHz. This allows a wide
range of output frequencies from 8 MHz to 200 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Block Diagram
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
TCLK0
0
TCLK1
1
TCLK_SEL
FB_IN
FB_SEL2
Phase
Detector
0
VCO 1
LPF
DQ
Sync
Frz
DQ
Sync
Frz
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
MR#/OE
SELA(0,1)
SELB(0,1)
SELC(0,1)
FB_SEL(0,1)
SCLK
SDATA
Power-On
Reset
2
2
2
2
/4,/6,/8,/12
/4,/6,/8,/10
/2/4,/6,/8
/4,/6,/8,/10
Sync Pulse
Data Generator
0
/2 1
Output Disable
12
Circuitry
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
QC0
QC1
QC2
QC3
FB_OUT
SYNC
INV_CLK
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.