AS7C3364PFS36A Datasheet, PDF (3/11 Pages) Alliance Semiconductor Corporation – 3.3V 64K X 32/36 pipeline burst synchronous SRAM

AS7C3364PFS32A
AS7C3364PFS36A
®
Signal descriptions
Signal
CLK
A0–A15
DQ[a,b,c,d]
I/
O Properties
I CLOCK
I SYNC
I/O SYNC
CE0
I SYNC
CE1, CE2 I SYNC
ADSP
ADSC
ADV
GWE
BWE
I SYNC
I SYNC
I SYNC
I SYNC
I SYNC
BW[a,b,c,d] I SYNC
OE
I ASYNC
STATIC
LBO
I default =
HIGH
FT
I STATIC
ZZ
I ASYNC
Description
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.¹⁸
Flow-through mode.When low, enables single register flow-through mode. Connect to V_DD
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
V_DD, V_DDQ
–0.5
V_IN
–0.5
V_IN
–0.5
P_D
–
I_OUT
–
T_stg
–65
T_bias
–65
+4.6
V
V_DD + 0.5
V
V_DDQ + 0.5
V
1.8
W
50
mA
+150
o_C
+135
o_C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
2/1/01
Alliance Semiconductor
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