AS7C3364PFS36A Datasheet, PDF (1/11 Pages) Alliance Semiconductor Corporation – 3.3V 64K X 32/36 pipeline burst synchronous SRAM

January 2001
Preliminary Information
AS7C3364PFS32A
AS7C3364PFS36A
®
3.3V 64K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 65,536 words × 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
• Pentium®^* compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• 30 mW typical standby power in power down mode
Logic block diagram
Pin arrangement
CLK
ADV
ADSC
ADSP
A[15:0]
16
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
Power
down
OE
Selection guide
LBO
CLK
CE
Q0
Burst logic
CLR
Q1
D
Q ¹⁶
14
CE
Address
register
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
64K × 32/36
16
Memory
array
36/32
36/32
4
OE
Output
registers
CLK
Input
registers
CLK
FT DATA [35:0]
DATA [31:0]
DQP_c/NC 1
DQ_c 2
DQ_c 3
V_DDQ 4
V_SSQ 5
DQ_c 6
DQ_c 7
DQ_c 8
DQ_c 9
V_SSQ 10
V_DDQ 11
DQ_c 12
DQ_c 13
FT 14
V_DD 15
NC 16
V_SS 17
DQ_d 18
DQ_d 19
V_DDQ 20
V_SSQ 21
DQ_d 22
DQ_d 23
DQ_d 24
DQ_d 25
V_SSQ 26
V_DDQ 27
DQ_d 28
DQ_d 29
DQP_d/NC 30
TQFP 14 × 20 mm
80 DQP_b/NC
79 DQ_b
78 DQb
77 VDDQ
76 VSSQ
75 DQ_b
74 DQb
73 DQ_b
72 DQ_b
71 VSSQ
70 VDDQ
69 DQ_b
68 DQ_b
67 V_SS
66 NC
65 VDD
64 ZZ
63 DQ_a
62 DQ_a
61 VDDQ
60 VSSQ
59 DQ_a
58 DQ_a
57 DQ_a
56 DQ_a
55 VSSQ
54 VDDQ
53 DQa
52 DQ_a
51 DQP_a/NC
Note: Pins 1,30,51,80 are NC for ×32
AS7C3364PFS32A AS7C3364PFS32A AS7C3364PFS32A AS7C3364PFS32A
–166
–150
–133
–100
Units
Minimum cycle time
6
6.7
7.5
10
ns
Maximum clock frequency
166
150
133
100
MHz
Maximum pipelined clock access time
3.5
3.8
4
5
ns
Maximum operating current
475
450
425
325
mA
Maximum standby current
130
110
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
mA
*_Pentium® _{is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this docu-}
ment are the property of their respective owners.
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