AS4C64M16D2-25BCN Datasheet, PDF (28/58 Pages) Alliance Semiconductor Corporation – 1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM)

AS4C64M16D2
NOTE 4: Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of
the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method
by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships
are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing
relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing
methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via
the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure proper
operation
NOTE 5: AC timings are for linear signal transitions.
NOTE 6:All voltages are referenced to VSS.
NOTE 7:These parameters guarantee device behavior, but they are not necessarily tested on each device.They may be
guaranteed by device design or tester correlation
NOTE 8: Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal
reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
Specific notes for dedicated AC parameters
NOTE 1:User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for
fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a
lower power value is defined by each vendor data sheet.
NOTE 2: AL=Additive Latency.
NOTE 3:This is a minimum requirement. Minimum read to precharge timing is AL+BL/2 provided that the tRTP and tRAS (min)
have been satisfied.
NOTE 4: A minimum of two clocks (2* tCK) is required irrespective of operating frequency.
NOTE 5: Timings are specified with command/address input slew rate of 1.0 V/ns.
NOTE 6:Timings are specified with DQs, DM, and DQS’s (in single ended mode) input slew rate of 1.0V/ns.
NOTE 7:Timings are specified with CK/CK# differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals
with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode.
NOTE 8:Data setup and hold time derating.
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet. tDS(base)
and tDH(base) value to the ∆tDS and ∆tDH derating value respectively.
Example: tDS (total setup time) =tDS (base) + ∆tDS.For slew rates in between the values listed in Tables 28, the derating
values may obtained by linear interpolation.These values are typically not subject to production test. They are verified
by design and characterization.
Table 24. DDR2-800 tDS/tDH derating with differential data strobe
DQ
Slew
Rate
V/ns
△tDS, △tDH derating values for DD2-800 (All units in ‘ps’; the note applies to the entire table)
DQS,DQS# Differential Slew Rate
4.0 V/ns
△tD △tD
S
H
3.0 V/ns
△tD △tD
S
H
2.0 V/ns
△tD △tD
S
H
1.8 V/ns
△tD △tD
S
H
1.6 V/ns
△tD △tD
S
H
1.4 V/ns
△tD △tD
S
H
1.2 V/ns
△tD △tD
S
H
2.0 100 45 100 45 100 45
-
-
-
-
-
-
-
-
1.5 67
21
67
21
67
21
79
33
-
-
-
-
-
-
1.0 0
0
0
0
0
0
12
12
24
24
-
-
-
-
0.9 -
-
-5
-14
-5
-14
7
-2
19
10
31
22
-
-
0.8 -
-
-
-
-13 -31
-1
-19
11
-7
23
5
35
17
0.7 -
-
-
-
-
-
-10 -42
2
-30
14
-18
26
-6
0.6 -
-
-
-
-
-
-
-
-10 -59
2
-47
14
-35
0.5 -
-
-
-
-
-
-
-
-
-
-24 -89 -12 -77
0.4 -
-
-
-
-
-
-
-
-
-
-
-
-52 -140
1.0 V/ns
△tD △tD
S
H
-
-
-
-
-
-
-
-
-
-
38
6
26
-23
0
-65
-40 -128
0.8 V/ns
△tD △tD
S
H
-
-
-
-
-
-
-
-
-
-
-
-
38 -11
12 -53
-28 -116
Alliance Memory Inc. reserves the right to change products or specification without notice.
27
Rev. 1.1
April. /2012