AS4C64M16D2-25BCN Datasheet, PDF (1/58 Pages) Alliance Semiconductor Corporation – 1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM)

AS4C64M16D2
1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Advanced (Rev. 1.0 April 2012)
Features
• JEDEC Standard Compliant
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Power supplies: VDD & VDDQ = +1.8V ± 0.1V
• Operating temperature:
- Commercial (0 ~ 85°C)
- Industrial (-40 ~ 95°C)
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 400MHz
• Differential Clock, CK & CK#
• Bidirectional single/differential data strobe
-DQS & DQS#
• 8 internal banks for concurrent operation
• 4-bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
• WRITE latency = READ latency - 1 tCK
• Burst lengths: 4 or 8
• Burst type: Sequential / Interleave
• DLL enable/disable
• On-die termination (ODT)
• RoHS compliant
• Auto Refresh and Self Refresh
• 8192 refresh cycles / 64ms
-Average refresh period
7.8µs @ 0℃≦TC≦+85℃
3.9µs @ +85℃＜TC≦+95℃
• 84-ball 8 x 12.5 x 1.2mm (max) FBGA package
- Pb and Halogen Free
Overview
The AS4C64M16D2 is a high-speed CMOS Double- Data-
Rate-Two (DDR2), synchronous dynamic random
- access memory (SDRAM) containing 1024 Mbits in a 16-
bit wide data I/Os. It is internally configured as a 8- bank
DRAM, 8 banks x 8Mb addresses x 16 I/Os.
The device is designed to comply with DDR2 DRAM key
features such as posted CAS# with additive latency, Write
latency = Read latency -1 and On Die Termination(ODT).
All of the control and address inputs are
synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential
clocks (CK rising and CK# falling)
All I/Os are synchronized with a pair of bidirectional
strobes (DQS and DQS#) in a source synchronous fashion.
The address bus is used to convey row, column, and bank
address information in RAS #, CAS# multiplexing style.
Accesses begin with the registration of a Bank Activate
command, and then it is followed by a Read or Write
command. Read and write accesses to the DDR2 SDRAM
are 4 or 8-bit burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence.
Operating the eight memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence. A sequential and gapless data rate is
possible depending on burst length, CAS latency, and
speed grade of the device.
Table 1. Ordering Information
Part Number
Clock Frequency
Data Rate
AS4C64M16D2-25BCN
400MHz
800Mbps/pin
AS4C64M16D2-25BIN
400MHz
800Mbps/pin
B: indicates 84-ball (8.0 x 12.5 x 1.2mm) FBGA package
C: indicates commercial temperature
I: indicates industrial temperature
N: indicates Pb and Halogen Free ROHS
Power Supply
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
Package
FBGA
FBGA
Table 2. Speed Grade Information
Speed Grade
Clock Frequency
DDR2-800
400 MHz
CAS Latency
5
tRCD (ns)
12.5
tRP (ns)
12.5
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: [phone]
FAX: [phone]
Alliance Memory Inc. reserves the right to change products or specification without notice.
1
Rev. 1.1
April. /2012