AS4C512M16D3L Datasheet, PDF (25/208 Pages) –

8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications
Input/Output Capacitance
Table 6: DDR3L Input/Output Capacitance
Note 1 applies to the entire table
Capacitance
Parameters
Sym
DDR3L
-800
Min Max
CK and CK#
ΔC: CK to CK#
Single-end
I/O: DQ, DM
C_CK
C_DCK
C_IO
0.8 1.6
0.0 0.15
1.4 2.5
Differential
I/O: DQS,
DQS#, TDQS,
C_IO
1.4 2.5
TDQS#
ΔC: DQS to
0.0 0.2
DQS#, TDQS, C_DDQS
TDQS#
ΔC: DQ to
DQS
–0.5 0.3
C_DIO
Inputs (CTRL,
CMD, ADDR)
C_I 0.75 1.3
ΔC: CTRL to
CK
–0.5 0.3
C_{DI_CTRL}
ΔC:
CMD_ADDR
–0.5
C_{DI_CMD}
0.5
to CK
_ADDR
ZQ pin
– 3.0
capacitance
C_ZQ
Reset pin
– 3.0
capacitance
C_RE
DDR3L
-1066
Min Max
0.8 1.6
0.0 0.15
1.4 2.5
1.4 2.5
0.0 0.2
–0.5 0.3
0.75 1.3
–0.5 0.3
–0.5 0.5
– 3.0
– 3.0
DDR3L
-1333
Min Max
0.8 1.4
0.0 0.15
1.4 2.3
1.4 2.3
0.0 0.15
–0.5 0.3
0.75 1.3
–0.4 0.2
–0.4 0.4
– 3.0
– 3.0
DDR3L
-1600
Min Max
0.8 1.4
0.0 0.15
1.4 2.2
1.4 2.2
0.0 0.15
–0.5 0.3
0.75 1.2
–0.4 0.2
–0.4 0.4
– 3.0
– 3.0
DDR3L
-1866
Min Max
0.8 1.3
0.0 0.15
1.4 2.1
1.4 2.1
0.0 0.15
–0.5 0.3
0.75 1.2
–0.4 0.2
–0.4 0.4
– 3.0
– 3.0
DDR3L
-2133
Min Max Unit Notes
0.8 1.3 pF
0.0 0.15 pF
2
1.4 2.1 pF
3
1.4 2.1 pF
0.0 0.15
3
pF
–0.5 0.3
4
pF
5
0.75 1.2 pF
–0.4 0.2
6
pF
–0.4 0.4
7
pF
–
3.0 _pF
–
3.0 _pF
Notes:
1. V_DD = 1.35V (1.283–1.45V), V_DDQ = V_DD, V_REF = V_SS, f = 100 MHz, T_C = 25°C. V_OUT(DC) = 0.5
× V_DDQ, V_OUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. C_DDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. C_DIO = C_IO(DQ) - 0.5 × (C_IO(DQS) + C_IO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. C_{DI_CTRL} = C_I(CTRL) - 0.5 × (C_CK(CK) + C_CK(CK#)).
7. C_{DI_CMD_ADDR} = C_{I(CMD_ADDR)} - 0.5 × (C_CK(CK) + C_CK(CK#)).
Rev.A 01/15EN
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