AS7C331MNTF18A Datasheet, PDF (15/18 Pages) Alliance Semiconductor Corporation – 3.3V 1M x 18 Flowthrough Synchronous SRAM with NTD

AS7C331MNTF18A
®
AC test conditions
• Output load: see Figure B, except for t_LZC, t_LZOE, t_HZOE, t_HZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.0V
90%
10%
GND
90%
10%
Figure A: Input waveform
D_OUT
Z₀ = 50Ω
50Ω
V_L = 1.5V
for 3.3V I/O;
30 pF* _{= VDDQ/2}
for 2.5V I/O
Figure B: Output load (A)
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
D_OUT
353Ω/1538Ω
319Ω/1667Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load(B)
Notes:
1) For test conditions, see “AC test conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t_HZOE is less than t_LZOE and t_HZC is less than t_LZC at any given temperature and voltage.
5) t_CH measured high above V_IH and t_CL measured as low below V_IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/W and BW[a,b].
8) Chip select refers to CE0, CE1, and CE2.
12/23/04, v 1.2
Alliance Semiconductor
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