AS7C33128PFD18B Datasheet, PDF (14/19 Pages) Alliance Semiconductor Corporation – 3.3V 128K x 18 pipeline burst synchronous SRAM

AS7C33128PFD18B
®
Timing waveform of read/write cycle (ADSC controlled, ADSP = HIGH)
CLK
t_ADSCS
ADSC
t_ADSCH
t_CYC
t_CH
t_CL
ADDRESS
A1
A2 A3 A4
GWE
t_CSS
CE0,CE2
t_CSH
t_AS
t_AH
A5 A6 A7 A8 A9
t_WS t_WH
CE1
ADV
OE
Dout
Din
t_OE
t_LZOE
Q(A1)
Q(A2)
t_HZOE
Q(A3)
Q(A4)
t_LZOE
t_OH
Q(A8)
Q(A9)
READ READ READ READ
Q(A1) Q(A2) Q(A3) Q(A4)
t_DS
t_DH
D(A5) D(A6)
D(A7)
WRITE WRITE ^WRITE READ ^READ
D(A5) D(A6) ^D(A7) Q(A8) ^Q(A9)
1/31/05; v.1.2
Alliance Semiconductor
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