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AS7C33128PFD18B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 128K x 18 pipeline burst synchronous SRAM | |||
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February 2005
AS7C33128PFD18B
®
3.3V 128K Ã 18 pipeline burst synchronous SRAM
Features
⢠Organization: 131,072 words à 18 bits
⢠Fast clock speeds to 200 MHz
⢠Fast clock to data access: 3.0/3.5/4.0 ns
⢠Fast OE access time: 3.0/3.5/4.0 ns
⢠Fully synchronous register-to-register operation
⢠Double-cycle deselect
⢠Asynchronous output enable control
⢠Available in 100-pin TQFP package
⢠Individual byte write and global write
⢠Multiple chip enables for easy expansion
⢠3.3V core power supply
⢠2.5V or 3.3V I/O operation with separate VDDQ
⢠Linear or interleaved burst control
⢠Snooze mode for reduced power-standby
⢠Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[16:0]
GWE
BWb
BWE
BWa
CE0
CE1
CE2
ZZ
OE
17
Power
down
LBO
CLK
CS Burst logic
CLR
D
Q
CS
Address
register
17
CLK
15 17
128K Ã 18
Memory
array
D DQb Q
Byte Write
registers
CLK
D DQa Q
Byte Write
registers
CLK
D Enable Q
register
CE
CLK
D Enable Q
delay
register
CLK
18 18
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ [a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
â200
5
200
3.0
375
130
30
â166
6
166
3.5
350
100
30
â133
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
1/31/05; v.1.2
Alliance Semiconductor
P. 1 of 19
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