AS4C8M32S Datasheet, PDF (14/55 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C8M32S
Table 3. Mode Register Bitmap
BA0,1 A11,A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
RFU* RFU* WBL Test Mode
CAS Latency
BT
Burst Length
A9 Write Burst Length
0
Burst
1
Single Bit
A8 A7
00
10
01
Test Mode
Normal
Vendor Use Only
Vendor Use Only
A3 Burst Type
0 Sequential
1 Interleave
A6 A5 A4 CAS Latency
A2 A1 A0
Burst Length
00 0
Reserved
0
0
0
1
00 1
Reserved
0
0
1
2
01 0
2 clocks
0
1
0
4
01 1
3 clocks
0
1
1
8
10 0
Reserved
1
1
1 Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
T0
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0, 1
A10
A0-A9,
A11
DQM
DQ ^Hi-Z
T1
T2 T3 T4 T5 T6
T7
T8
t_MRD
Address Key
t_RP
PrechargeAll
Mode Register
Set Command
Any
Command
T9
T10
Don’t Care
Figure 15. Mode Register Set Cycle
Alliance Memory Confidential
13
Rev. 2.0 May /2014