AS7C33256PFD32A Datasheet, PDF (1/20 Pages) Alliance Semiconductor Corporation – 3.3V 256K x 32/36 pipelined burst synchronous SRAM

December 2004
AS7C33256PFD32A
AS7C33256PFD36A
®
3.3V 256K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Asynchronous output enable control
• Available in100-pin TQFP
• Individual byte write and global write
• Multiple chip enables for easy expansion
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
Logic block diagram
CLK
ADV
ADSC
ADSP
A[17:0]
BWE
GWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
OE
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
18
Power
down
LBO
CLK
CE
Q0
Burst logic
CLR
Q1
D
Q ^{18 2 16 2 18}
CE
Address
register
CLK
256K × 32/36
Memory
array
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
36/32
36/32
4
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
OE
Output
registers
CLK
Input
registers
CLK
36/32
DQ[a:d]
–166
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
12/1/04, v.1.2
Alliance Semiconductor
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