AS4LC8M8S0 Datasheet, PDF (1/24 Pages) Alliance Semiconductor Corporation – 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

Advance information
AS4LC8M8S0
AS4LC4M16S0
®
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
• PC100/133 compliant
• Organization
- 2,097,152 words × 8 bits × 4 banks (8M×8)
- 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous
- All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/BA1 (bank select)
• High speed
- 133/125/100 MHz
- 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
• Low power consumption
- Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 54-pin TSOP II
• Read/write data masking
• Programmable burst length (1/2/4/8/full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (2/3)
Pin arrangement
AS4LC4M16S0
V_CC
V_CC
1
DQ0
V_CCQ
DQ0
2
V_CCQ
3
NC
DQ1
4
DQ1
DQ2
5
V_SSQ
V_SSQ
6
NC
DQ3
7
DQ2
V_CCQ
DQ4
8
V_CCQ
9
NC
DQ5
10
DQ3
DQ6
11
V_SSQ
V_SSQ
12
NC
DQ7
13
V_CC
V_CC
14
NC LDQM 15
WE
WE
16
CAS
CAS
17
RAS
RAS
18
CS
CS
19
BA0
BA0
20
BA1
BA1
21
A10
A10
22
A0
A0
23
A1
A1
24
A2
A2
25
A3
A3
26
V_CC
V_CC
27
54
V_SS
V_SS
53 DQ15 DQ7
52
V_SSQ
V_SSQ
51
DQ14
NC
50
DQ13
DQ6
49
V_CCQ
V_CCQ
48 DQ12 NC
47
DQ11
DQ5
46
V_SSQ
V_SSQ
45
DQ10
NC
44 DQ9
DQ4
43
V_CCQ
V_CCQ
42 DQ8
NC
41
V_SS
V_SS
40 NC
NC
39 UDQM DQM
38 CLK
CLK
37 CKE
CKE
36 NC
NC
35 A11
A11
34 A9
A9
33 A8
A8
32 A7
A7
31 A6
A6
30 A5
A5
29 A4
A4
28
V_SS
V_SS
AS4LC4M16S0
Pin designation
Pin(s)
DQM (8M×8)
UDQM/LDQM (4M×16)
A0 to A11
BA0, BA1
DQ0 to DQ7 (8M×8)
DQ0 to DQ15 (4M×16)
RAS
CAS
WE
CS
V_CC, V_CCQ
V_SS, V_SSQ
CLK
CKE
Description
Output disable/write mask
Address inputs
Bank select inputs
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
Selection guide
Bus frequency
CL = 2
Minimum clock access time
CL = 3
Minimum setup time
Minimum hold time
Minimum RAS to CAS delay
Minimum RAS precharge time
Remarks: (CL/t_RCD/t_RP)
Symbol
f_max
t_AC
t_AC
t_S
t_H
t_RCD
t_RP
-75 (PC133)
133
–
5.4
1.5
0.8
3
3
3/3/3
-8
125
–
6
2
1.0
3
3
3/3/3
-10F (PC100)
100
6
–
2
1.0
2
2
2/2/2
-10 (PC100)
100
–
6
2
1.0
3
3
3/3/3
Unit
MHz
ns
ns
ns
ns
cycles
cycles
7/5/00
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