A4984_12 Datasheet, PDF (9/22 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator And Overcurrent Protection

A4984
DMOS Microstepping Driver with Translator
And Overcurrent Protection
Direction Input (DIR). This determines the direction of rota-
tion of the motor. Changes to this input do not take effect until the
next STEP rising edge.
Internal PWM Current Control. Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, I_TRIP. Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows
through the motor winding and the current sense resistor, R_Sx.
When the voltage across R_Sx equals the DAC output voltage, the
current sense comparator resets the PWM latch. The latch then
turns off either the source FET (when in Slow decay mode) or the
sink and source FETs (when in Mixed decay mode).
The maximum value of current limiting is set by the selection of
R_Sx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
I_TripMAX (A), which is set by
 I_TripMAX = V_REF / ( 8 R_S)
where R_S is the resistance of the sense resistor (Ω) and V_REF is
the input voltage on the REF pin (V).
The DAC output reduces the V_REF output to the current sense
comparator in precise steps, such that
× ^Itrip ^{= (%I}TripMAX ^{/ 100) I}TripMAX
(See table 2 for %I_TripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, t_BLANK (μs), is approximately
t_BLANK ≈ 1 μs
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is
shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protect-
ing the device from damage. In the case of a short-to-ground, the
device will remain disabled (latched) until the S¯¯L¯¯E¯¯E¯¯P input goes
high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 4.
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time (≈1 μs) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into
a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in figure 5.
If the driver is operating in Mixed decay mode, it is normal for
the positive current to spike, due to the bridge going in the for-
ward direction and then in the negative direction, as a result of the
direction change implemented by the Mixed decay feature. This
is shown in figure 6. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The off-time, t_OFF, is determined by the
ROSC terminal. The ROSC terminal has three settings:
▪ ROSC tied to VDD — off-time internally set to 30 μs, decay
mode is automatic Mixed decay except when in full step where
decay mode is set to Slow decay
▪ ROSC tied directly to ground — off-time internally set to
30 μs, current decay is set to Mixed decay for both increasing
and decreasing currents for all step modes.
▪ ROSC through a resistor to ground — off-time is determined
by the following formula, the decay mode is automatic Mixed
decay for all step modes.
t_OFF ≈ R_OSC ⁄ 825
Where t_OFF is in μs.
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
V_REG (VREG). This internally-generated voltage is used to
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. V_REG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4984 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
Allegro MicroSystems, Inc.
9
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com