A4984_12 Datasheet, PDF (18/22 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator And Overcurrent Protection

A4984
ES Package
DMOS Microstepping Driver with Translator
And Overcurrent Protection
Pin-out Diagrams
ET Package
LP Package
OUT2B 1
ENABLE 2
GND 3
CP1 4
CP2 5
VCP 6
PAD
18 OUT1B
17 DIR
16 GND
15 REF
14 STEP
13 VDD
OUT2B 1
NC 2
VBB2 3
NC 4
ENABLE 5
GND 6
CP1 7
CP2 8
PAD
24 OUT1B
23 NC
22 VBB1
21 NC
20 DIR
19 GND
18 REF
17 STEP
CP1 1
CP2 2
VCP 3
VREG 4
MS1 5
MS2 6
RESET 7
ROSC 8
SLEEP 9
VDD 10
STEP 11
REF 12
PAD
24 GND
23 ENABLE
22 OUT2B
21 VBB2
20 SENSE2
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND
Terminal List Table
Name
Number
ES
ET*
LP
Description
CP1
4
7
1
Charge pump capacitor terminal
CP2
5
8
2
Charge pump capacitor terminal
DIR
17
20
14
Logic input
¯E¯ ¯N¯ ¯A¯ ¯B¯ ¯L¯ ¯E¯
2
5
23
Logic input
GND
3, 16
6, 19
13, 24 Ground
MS1
8
11
5
Logic input
MS2
9
12
6
Logic input
NC
–
2, 4, 21, 23,
26, 28, 29, 31
–
No connection
OUT1A
21
27
18
DMOS Full Bridge 1 Output A
OUT1B
18
24
15
DMOS Full Bridge 1 Output B
OUT2A
22
30
19
DMOS Full Bridge 2 Output A
OUT2B
1
1
22
DMOS Full Bridge 2 Output B
REF
15
18
12
G_m reference voltage input
¯R¯ ¯E¯ ¯S¯ ¯E¯ ¯T¯
10
13
7
Logic input
ROSC
11
14
8
Timing set
SENSE1
20
25
17
Sense resistor terminal for Bridge 1
SENSE2
23
32
20
Sense resistor terminal for Bridge 2
¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯
12
15
9
Logic input
STEP
14
17
11
Logic input
VBB1
19
22
16
Load supply
VBB2
24
3
21
Load supply
VCP
6
9
3
Reservoir capacitor terminal
VDD
13
16
10
Logic supply
VREG
7
10
4
Regulator decoupling terminal
PAD
–
–
–
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
Allegro MicroSystems, Inc.
18
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com